This invention relates to a method of manufacture of an active matrix device, especially an active matrix liquid crystal display (AMLCD), wherein the device comprises a row and column array of active elements, and wherein each element is associated with a self-aligned, top gate (TG) thin film transistor (TFT) connected to corresponding row and column conductors.
A conventional AMLCD is shown schematically in FIG. 1. The AMLCD 10 comprises an display area 11 consisting of m rows (1 to m) and n columns (1 to n) of identical picture elements 12. Only a few of the picture elements are shown for simplicity whereas in practice, the total number of picture elements (mxc3x97n) in the display area may be 200,000 or more. Each picture element 12 has a picture electrode 13 and associated therewith a switching TFT 14 which serves to control the application of data signal voltages to the picture electrode. The switching TFTs have common operational characteristics and are each arranged adjacent to their associated picture element with their respective drain being connected to the picture electrode. The sources of all switching TFTs associated with one column of picture elements are connected to a respective one of a set of parallel column conductors 15 and the gates of all switching TFTs associated with one row of picture elements are connected to a respective one of a set of parallel row conductors 16. The TFTs 13 are controlled by gating signals provided via the row conductors by row driver circuitry 17 external to the display area 11. Similarly, the TFTs associated with picture elements in the same column are provided with data signal voltages for the picture electrodes by column driver circuitry 18 also external to the display panel. Of course, the operation of picture elements in such AMLCDs is well known and further described in our U.S. Pat. No. 5,130,829, and accordingly will not be elaborated upon here further.
During the manufacture of such an AMLCD, it is desirable to keep the capacitance of the switching TFTs to a minimum and one way of achieving this is to use self-aligned TFTs as the switching TFTs. Furthermore, using self-aligned TFTs does not require any increase in the mask count to achieve said reduction in capacitance.
FIGS. 2A to 2D show schematically a known process for producing a self-aligned TFT 14 requiring 4 photomask steps and a single back exposure. The process comprises the steps of forming opaque source 22 and drain electrodes 22xe2x80x2 on a transparent substrate 21 (mask 1); forming an amorphous silicon semiconductor channel 23 so as to join the source and drain electrodes, and a first gate insulating layer 24 thereon (mask 2); forming a second gate insulating layer 25 (mask 3); depositing a layer of transparent gate material, typically indium tin oxide (ITO), and patterning the material by back exposure so as to form the gate electrode 26; and forming a gate contact 28 (mask 4). The transparent gate material may be patterned by providing a negative resist layer (not shown) over the material and selectively exposing it to UV radiation from beneath the substrate 21. The source and drain electrodes 22, 22xe2x80x2 shield the UV light, so that the passage of light through the transistor structure only takes place in the spacing between the source and drain electrodes. The UV light diffracts and scatters as it passes through this opening, and results in source/drain overlap 27 wherein the exposed region of the resist layer is wider than the spacing between the source and drain electrodes. Source/drain overlap is useful in that the gate electrode may then modulate the whole of the semiconductor channel area. The overlap may be alternatively provided, inter alia, by overexposing the photoresist.
In order to realise the benefits of using self-aligned TFTs, the method of manufacturing the self-aligned TFTs must be incorporated into the whole picture element manufacturing process.
FIG. 3 shows, schematically, a conventional picture element 12 comprising a self aligned TFT of the type whose the manufacture is illustrated in FIGS. 2A to 2D. The picture element comprises 6 regions: a conductor crossover (R1, R1xe2x80x2); the self-aligned TG TFT (R2); a first transparent pixel electrode contact (R3); a transparent pixel electrode (R4); a capacitor (R5); and a second transparent pixel electrode contact (R6).
In addition, a known 6 photomask single back exposure method of manufacturing the picture element 12 of FIG. 3 is illustrated in FIGS. 4A to 4C wherein FIGS. 4A to 4C are cross sections of the picture element of FIG. 3 along lines A1-A2-A3-A4 and A3-A5.
Referring to FIG. 4A, the method comprises the steps of forming a transparent pixel electrode 32, typically ITO, on a transparent substrate 21 (mask 1); forming opaque source 22 and drain electrodes 22xe2x80x2, and column conductors 15, part of which act a capacitor plate 15xe2x80x2 and a pixel electrode contact 15xe2x80x3 (mask 2); and forming a semiconductor channel layer 23 so as to join the source and drain electrodes, and a first gate insulating layer 24 thereon. Referring to FIG. 4B, a second gate insulating layer 25 is formed (mask 4) and a layer of transparent gate material deposited, typically ITO, and patterned by a back exposure so as to form the gate electrode 26 (back exposure plus mask 5). Mask 5 is required so as not to etch away the pixel electrode 32 whilst patterning the gate electrode 26. Lastly, as shown in FIG. 4C, a gate contact 28 and gate row conductors 16 are formed (mask 6).
It is an object of the invention to provide a simplified method of manufacturing an active matrix device, especially an AMLCD, using self-aligned TFT switching as described above.
In accordance with the present invention, there is provided a method of manufacturing an active matrix device comprising a row and column array of active elements wherein each element comprises a transparent pixel electrode associated with a self-aligned, top gate transistor having a transparent gate electrode, and an active matrix device manufactured using the same. The method comprises the steps of:
forming opaque source and drain electrodes on a transparent substrate;
forming a semiconductor channel layer so as to join source and drain electrodes;
forming an insulating layer, at least part of which comprises the gate dielectric; and
depositing a transparent conductive layer over the insulating layer and forming both the transparent gate electrode and the transparent pixel electrode therefrom.
The present invention provides a manufacturing process for active matrix devices with a reduced mask count compared to known methods. This is, at least in part, attributable to the manufacture of the transparent gate electrode and the transparent pixel electrode from the same deposited layer.
Conveniently, the transparent gate electrode is formed by depositing a layer of negative resist over the transparent conductive layer, exposing the layer of negative resist through the substrate such that regions of the negative resist shadowed by the opaque electrodes remain unexposed, removing the unexposed negative and, having masked the region associated with the transparent pixel electrode, removing the exposed transparent conductive layer.
The pixel electrode may be formed over the insulating layer so as to reducing the amount of etching of the insulating layer required and in which case, the insulting layer may include etched contact holes so as to enable the drain electrode to be connected to the transparent pixel electrode.
Further provided in accordance with the present invention is an active matrix device comprising a row and column array of active elements wherein each element comprises opaque source and drain electrodes on a transparent substrate; a semiconductor channel layer joining the source and drain electrodes; an insulating layer, at least part of which comprises a gate dielectric; and transparent pixel and gate electrodes, both of which positioned over the insulating layer.